(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of achieving a bridging-free salicide and low resistance interconnect process in the fabrication of integrated circuits.
(2) Description of the Prior Art
As the feature sizes shrink in the fabrication of VLSI integrated circuit devices to the deep submicron regime, contact resistance increases and sheet resistivity of the source/drain regions increases. As discussed in Silicon Processing for the VLSI Era, Vol. 1, by Stanley Wolf and Richard N. Tauber, Lattice Press, Sunset Beach, Calif., c. 1986, pp.397-399, self-aligned silicide (salicide) technology is used to reduce contact resistance. Titanium salicide is widely used, but has the disadvantage of bridging; that is, the shorting of the gate electrode to the source/drain. This is especially a problem in the deep submicron regime where the sidewall spacer on the gate may be less than about 1000 Angstroms thick.
Wolf and Tauber discuss annealing the titanium in a nitrogen ambient to suppress lateral silicide reaction and thus avoid bridging. U.S. Pat. No. 5,231,038 to Yamaguchi et al also teach annealing in a nitrogen atmosphere.